1. Field of the Invention
The present invention relates to the field of Dynamic Random Access Memory. Specifically, the present invention relates to the addressing of Dynamic Random Access Memories.
2. Art Background
A computer system requires memory for storing data and program instructions. There are different types of memories using different technologies and having different utility in the computer system. A random access memory (RAM) is one in which the time required for writing information and reading information is independent of the physical location within the memory.
A RAM memory chip is composed of a matrix of cells which stores the bits of information written to the memory. In a static RAM (SRAM) flip-flops are utilized as the storage cells. In a Dynamic RAM (RAM), data is stored on capacitors, resulting in a reduction in cell area.
The bits on a memory chip are either individually addressable or addressable in groups of a predetermined size such as four or eight bits. The memory is addressed by providing a row address which selects the row of the matrix and a column address which selects the column of the matrix at which memory operation is to take place.
Various techniques have been developed to improve the speed of access to the memory. In one technique, buffers or latches are provided for each bank or array of memory. The row address is applied to the memory array to access the row of memory. The row is placed in the row latch for that array. The column address is then applied to the latch to access the particular column of the row requested. Subsequent accesses to the same row but a different column are quickly performed by applying the column address to the latch.
In DRAM devices, row sense amplifier latches are provided to buffer a row from a bank of memory. The row sense amplifier senses the row driven by the row address strobe and maintains the row information until a subsequent row in the memory is driven.
Although buffering improves the speed of access to the array, due to spatial and temporal locality of the data accesses, the spatial and temporal locality also function to increase the latency due to the frequency of access of different rows in the same array. Therefore excessive contention for the latch will result. As the accesses are directed to the one array, the latches for other arrays of the memory will be underutilized. In time, the accessing pattern will shift to a different memory array and a different latch will experience the excessive contention.